This invention relates generally to computer processor operation, and more particularly to providing a method, system, and computer program product for merging data.
Modern computer systems may include multiple (e.g., two or more) processors and corresponding multiple level cache memories (or “caches”) that store recently accessed data so that it can be quickly accessed again by a processor without the time delay (or “latency”) resulting from having to access the main memory (or “memory”) for the data. A multi-level cache may include a low level (or “L1”) cache and higher level (e.g., “L2”, “L3”, etc.) caches, where the lower the level of the cache, the more quickly accessible it is by a processor. In such computer systems, manipulating (e.g., accessing and/or modifying) of input/output (“I/O”) data in various increments, such as smaller than a standard memory block size, (or “merging”) involves using (e.g., accessing and/or utilizing) a memory controller. Merging of I/O data is done by the memory controller by either: a) accessing data from the memory (when a copy of the data does not exist in the multi-level cache), merging the data, and then writing the data back to the memory; or b) removing (or “evicting”) a copy of data from the cache to the memory controller, merging the data, then writing the data to the memory. These approaches for merging data are typically desirable for computer systems that include I/O devices that have direct access to a system connection (or “bus”) and can be relatively easily routed to the memory controller.
However, the above described approaches are less desirable for multi-processor computer systems that include a shared level cache, such as the L2 cache, through which I/O components are directly and/or continuously attached. For example, application of these approaches for such shared cache configurations involves relatively long processing times to complete the I/O data manipulation for merging, which may include complex manipulation. Also, using the memory controller in these approaches causes an increased utilization of memory resources and the undesirable eviction of memory blocks that contain data (such control or instruction blocks) that needs to be commonly updated by I/O devices and the multi-processors. Therefore, a high performance approach to merging of data from I/O devices without incurring the additional latency resulting from using a memory controller is desirable.